FAN7385 Datasheet, PDF (13/15 Pages) Fairchild Semiconductor – Dual-Channel High-Side Gate-Drive IC

Typical Application Information
1. Under-Voltage Lockout (UVLO)
The FAN7385 has an under-voltage lockout (UVLO)
protection circuit to prevent malfunction when V_BS1 and
V_BS2 are lower than the specified threshold voltage. The
UVLO circuit monitors the bootstrap capacitor voltages
(V_BS1, V_BS2) independently.
2. Layout Consideration
For optimum performance, considerations must be given
during printed circuit board (PCB) layout.
2.1 Supply Capacitors
If the output stages are able to quickly turn on a switch-
ing device with a high current value, the supply capaci-
tors must be placed as close as possible to the device
pins (V_DD and GND for the ground-tied supply, V_B and
V_S for the floating supply) to minimize parasitic induc-
tance and resistance.
2.2 Gate Drive Loop
Current loops behave like antennae, able to receive and
transmit noise. To reduce the noise coupling/emission
and improve the power switch turn-on and off perfor-
mances, gate drive loops must be reduced as much as
possible.
2.3 Ground Plane
To minimize noise coupling, avoid placing the ground
plane under or near the high-voltage floating side.
© 2006 Fairchild Semiconductor Corporation
FAN7385 Rev. 1.0.2
13
www.fairchildsemi.com