FAN4800_06 Datasheet, PDF (13/20 Pages) Fairchild Semiconductor – Low Start-Up Current PFC/PWM Controller Combos

1.10 Example
For the application circuit shown in Figures 12 and 13,
with the oscillator running at:
f_OSC
= 100kHz
=
1
t_RAMP
(12)
solving for C_T x R_T yields 1.96 x 10^-4. C_T is 390pF and
R_T is 51.1kΩ, selecting standard components values.
The dead time of the oscillator adds to the maximum
PWM duty cycle (it is an input to the duty cycle limiter).
With zero oscillator dead time, the maximum PWM duty
cycle is typically 47%. Take care not to make C_T too
large, which could extend the maximum duty cycle
beyond 50%. This can be accomplished by using no
greater than a 390pF capacitor for C_T.
2. PWM Section
2.1 Pulse Width Modulator (PWM)
The operation of the PWM section of the FAN4800 is
straightforward, but there are several points that should
be noted. Foremost among these is the inherent syn-
chronization of PWM with the PFC section of the device,
from which it also derives its basic timing. The PWM is
capable of current-mode or voltage-mode operation. In
current-mode applications, the PWM ramp (RAMP2) is
usually derived directly from a current sensing resistor or
current transformer in the primary of the output stage. it
is thereby representative of the current flowing in the
converter’s output stage. DC I_LIMIT, which provides cycle-
by-cycle current limiting, is typically connected to
RAMP2 in such applications. For voltage-mode opera-
tion and certain specialized applications, RAMP2 can be
connected to a separate RC timing network to generate
a voltage ramp against which V_DC is compared. Under
these conditions, the use of voltage feed-forward from
the PFC bus can assist in line regulation accuracy and
response. As in current-mode operation, the DC I_LIMIT
input is used for output stage over-current protection.
No voltage error amplifier is included in the PWM stage
of the FAN4800, as this function is generally performed
on the output side of the PWM’s isolation boundary. To
facilitate the design of opto-coupler feedback circuitry, an
offset has been built into the PWM’s RAMP2 input that
allows V_DC to command a 0% duty cycle for input volt-
ages below typical 0.9V.
2.2 PWM Current Limit
The DC I_LIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output flip-flop is
reset by the clock pulse at the start of the next PWM
power cycle. When the DC I_LIMIT triggers the cycle-by-
cycle current, it also softly discharges the voltage of the
soft-start capacitor. It limits the PWM duty cycle mode
and the power dissipation is reduced during the dead-
short condition.
2.3 V_IN OK Comparator
The V_IN OK comparator monitors the DC output of the
PFC and inhibits the PWM if the voltage on V_FB is less
than its nominal 2.25V. Once the voltage reaches 2.25V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start begins.
2.4 PWM Control (RAMP2)
When the PWM section is used in current mode, RAMP2
is generally used as the sampling point for a voltage,
representing the current in the primary of the PWM’s out-
put transformer. The voltage is derived either from a cur-
rent sensing resistor or a current transformer. In voltage
mode, RAMP2 is the input for a ramp voltage generated
by a second set of timing components (R_RAMP2, C_RAMP2)
that have a minimum value of 0V and a peak value of
approximately 5V. In voltage mode, feed forward from
the PFC output bus is an excellent way to derive the tim-
ing ramp for the PWM stage.
2.5 Soft-Start (SS)
PWM start-up is controlled by selection of the external
capacitor at soft-start. A current source of 20mA supplies
the charging current for the capacitor and start-up of the
PWM begins at 0.9V. Start-up delay can be programmed
by the following equation:
C_SS
=
t_DELAY
× ^20μA
0.9V
(13)
where C_SS is the required soft-start capacitance and the
t_DELAY is the desired start-up delay.
It is important that the time constant of the PWM soft-
start allows the PFC time to generate sufficient output
power for the PWM section. The PWM start-up delay
should be at least 5ms.
Solving for the minimum value of C_SS:
C_SS
=
5ms ×
20μA
0.9V
= 111nF
(14)
Use caution when using this minimum soft-start capaci-
tance value because it can cause premature charging of
the SS capacitor and activation of the PWM section if
V_FB is in the hysteresis band of the V_IN OK comparator
at start-up. The magnitude of V_FB at start-up is related
both to line voltage and nominal PFC output voltage.
Typically, a 1.0µF soft-start capacitor allows time for V_FB
and PFC_OUT to reach their nominal values prior to acti-
vation of the PWM section at line voltages between
90Vrms and 265Vrms.
© 2005 Fairchild Semiconductor Corporation
FAN4800 Rev. 1.0.5
13
www.fairchildsemi.com