FXLA104_12 Datasheet, PDF (12/18 Pages) Fairchild Semiconductor – Low-Voltage Dual-Supply 4-Bit Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing

I/O Architecture Benefit
The FXLA104 I/O architecture benefits the end user,
beyond level translation, in the following three ways:
Auto Direction without an external direction pin.
Drive Capacitive Loads. Automatically shifts to a
higher current drive mode only during “Dynamic Mode”
or HL / LH transitions.
Lower Power Consumption. Automatically shifts to
low-power mode during “Static Mode” (no transitions),
lowering power consumption.
The FXLA104 does not require a direction pin. Instead,
the I/O architecture detects input transitions on both
side and automatically transfers the data to the
corresponding output. For example, for a given channel,
if both A and B side are at a static LOW, the direction
has been established as A  B, and a LH transition
occurs on the B port; the FXLA104 internal I/O
architecture automatically changes direction from A  B
to B  A.
During HL / LH transitions, or “Dynamic Mode,” a strong
output driver drives the output channel in parallel with a
weak output driver. After a typical delay of
approximately 10ns – 50ns, the strong driver is turned
off, leaving the weak driver enabled for holding the logic
state of the channel. This weak driver is called the “bus
hold.” “Static Mode” is when only the bus hold drives the
channel. The bus hold can be over ridden in the event
of a direction change. The strong driver allows the
FXLA104 to quickly charge and discharge capacitive
transmission lines during dynamic mode. Static mode
conserves power, where I_CC is typically < 5µA.
Bus Hold Minimum Drive Current
Specifies the minimum amount of current the bus hold
driver can source/sink. The bus hold minimum drive
current (II_HOLD) is V_CC dependent and guaranteed in the
DC Electrical tables. The intent is to maintain a valid
output state in a static mode, but that can be overridden
when an input data transition occurs.
Bus Hold Input Overdrive Drive Current
Specifies the minimum amount of current required (by
an external device) to overdrive the bus hold in the
event of a direction change. The bus hold overdrive
(II_ODH, II_ODL) is V_CC dependent and guaranteed in the DC
Electrical tables.
Dynamic Output Current
The strength of the output driver during LH / HL
transitions is referenced on page 8, Dynamic Output
Electrical Characteristics, I_OHD, and I_OLD.
© 2009 Fairchild Semiconductor Corporation
FXLA104 • Rev. 1.0.9
12
www.fairchildsemi.com