FDMF6824C Datasheet, PDF (12/19 Pages) Fairchild Semiconductor – FDMF6824C — Extra-Small, High-Performance, High-Frequency DrMOS Module

Functional Description
The FDMF6824C is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each part is
capable of driving speeds up to 1 MHz.
VCIN and Disable (DISB#)
The VCIN pin is monitored by an Under-Voltage Lockout
(UVLO) circuit. When V_CIN rises above ~3.1 V, the driver
is enabled. When V_CIN falls below ~2.7 V, the driver is
disabled (GH, GL=0). The driver can also be disabled by
pulling the DISB# pin LOW (DISB# < V_{IL_DISB}), which
holds both GL and GH LOW regardless of the PWM
input state. The driver can be enabled by raising the
DISB# pin voltage HIGH (DISB# > V_{IH_DISB}).
Table 1. UVLO and Disable Logic
UVLO DISB#
Driver State
0
X
1
0
Disabled (GH, GL=0)
Disabled (GH, GL=0)
1
1
Enabled (see Table 2)
1
Open
Disabled (GH, GL=0)
Note:
3. DISB# internal pull-down current source is 10 µA.
Thermal Warning Flag (THWN#)
The FDMF6824C provides a thermal warning flag
(THWN#) to warn of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN# output returns to a high-
impedance state once the temperature falls to the reset
temperature (135°C). For use, the THWN# output
requires a pull-up resistor, which can be connected to
VCIN. THWN# does NOT disable the DrMOS module.
THWN#
Logic
State
HIGH
135°C Reset ^150°C
Temperature ^Activation
Temperature
Normal
Operation
Thermal
Warning
LOW
T_{J_driver IC}
Figure 26. THWN Operation
Three-State PWM Input
The FDMF6824C incorporates a three-state 5V PWM
input gate drive design. The three-state gate drive has
both logic HIGH level and LOW level, along with a
three-state shutdown window. When the PWM input
signal enters and remains within the three-state window
for a defined hold-off time (t_{D_HOLD-OFF}), both GL and GH
are pulled LOW. This enables the gate drive to shut
down both high-side and low-side MOSFETs to support
features such as phase shedding, which is common on
multi-phase voltage regulators.
Exiting Three-State Condition
When exiting a valid three-state condition, the
FDMF6824C follows the PWM input command. If the
PWM input goes from three-state to LOW, the low-side
MOSFET is turned on. If the PWM input goes from
three-state to HIGH, the high-side MOSFET is turned
on. This is illustrated in Figure 27. The FDMF6824C
design allows for short propagation delays when exiting
the three-state window (see Electrical Characteristics).
Low-Side Driver
The low-side driver (GL) is designed to drive a ground-
referenced, low-R_DS(ON), N-channel MOSFET. The bias
for GL is internally connected between the VDRV and
CGND pins. When the driver is enabled, the driver's
output is 180° out of phase with the PWM input. When
the driver is disabled (DISB#=0 V), GL is held LOW.
High-Side Driver
The high-side driver (GH) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit
consisting of the internal Schottky diode and external
bootstrap capacitor (C_BOOT). During startup, V_SWH is held
at PGND, allowing C_BOOT to charge to V_DRV through the
internal diode. When the PWM input goes HIGH, GH
begins to charge the gate of the high-side MOSFET (Q1).
During this transition, the charge is removed from C_BOOT
and delivered to the gate of Q1. As Q1 turns on, V_SWH
rises to V_IN, forcing the BOOT pin to V_IN + V_BOOT, which
provides sufficient V_GS enhancement for Q1. To complete
the switching cycle, Q1 is turned off by pulling GH to
V_SWH. C_BOOT is then recharged to V_DRV when V_SWH falls to
PGND. GH output is in-phase with the PWM input. The
high-side gate is held LOW when the driver is disabled or
the PWM signal is held within the three-state window for
longer than the three-state hold-off time, t_{D_HOLD-OFF}.
© 2013 Fairchild Semiconductor Corporation
FDMF6824C • Rev. 1.0.1
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