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FAN6961 Datasheet, PDF (12/13 Pages) Fairchild Semiconductor – Boundary Mode PFC Controller
Physical Dimensions (Continued)
5.00
4.80
3.81
8
A
5
B
6.20
5.80
4.00
3.80
1.75
0.65
5.60
PIN ONE
1
INDICATOR
(0.33)
4
1.27
0.25 M C B A
1.27
LAND PATTERN RECOMMENDATION
1.75 MAX
R0.10
R0.10
8°
0°
0.90
0.406
0.25
0.10
C
SEE DETAIL A
0.25
0.19
0.51
0.33
0.10 C
0.50
0.25
x
45°
GAGE PLANE
0.36
OPTION A - BEVEL EDGE
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
Figure 16. 8-Lead, SOIC,JEDEC MS-012, .150 Inch Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
FAN6961 • Rev. 1.0.2
12
www.fairchildsemi.com