FAN6747 Datasheet, PDF (12/15 Pages) Fairchild Semiconductor – Highly Integrated Green-Mode PWM Controller

Operation Description
Startup Current
For startup, the HV pin is connected to the line input
through an external diode and resistor, RHV, (1N4007 /
200KΩ recommended). Peak startup current drawn from
the HV pin is (VAC × 2 )/RHV and charges the hold-up
capacitor through the diode and resistor. When the VDD
capacitor level reaches VDD-ON, the startup current
switches off. At this moment, the VDD capacitor only
supplies the FAN6747 to maintain the VDD before the
auxiliary winding of the main transformer provides the
operating current.
Operating Current
Operating current is around 2mA. The low operating
current enables better efficiency, power saving, and
reduces the requirement of VDD hold-up capacitance.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to reduce the switching frequency in light-
load and no-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference.
Once VFB is lower than the threshold voltage, switching
frequency is continuously decreased to the minimum
green-mode frequency of around 22KHz.
Two-Level Over-Current Protection (OCP)
The cycle-by-cycle current limiting shuts down the PWM
immediately when the sense voltage is over the limited
threshold voltage (0.825V at low line). Additionally,
when the sense voltage is higher than the OCP
threshold (0.48V at low line), the internal counter counts
for 220ms, then latches off PWM. When OCP occurs,
PWM output is turned off and VDD begins decreasing.
When VDD goes below the turn-off threshold (~9V), the
controller is totally shut down. VDD continues to
discharge below VDD-OLP by IDD-OLP. Then VDD is charged
up to the turn-on threshold voltage of 16.5V through the
startup resistor. When VDD is charged to 16.5V, it cycles
again. This phenomenon is called two-level UVLO.
Brownout and Constant Power Limited
HV Pin
Unlike previous PWM controllers, FAN6747’s HV pin
isn’t only used for startup; it can also detect the AC line
voltage to perform brownout function and set the current
limit level. Through a fast diode and startup resistor to
sample the AC line voltage, the peak value refreshes
and stores in register at each sampling cycle. When
internal update time is met, this peak value is used to for
brownout and current-limit level judgment. Equations 1
and 2 can be used to calculate out the level of brown-in
or brownout converted to RMS value. For power saving,
FAN6747 enlarges the sampling cycle to lower the
power loss from HV sampling at light-load condition.
V_{AC −ON}
(RMS
)
=
(0.9
×
R_HV + 1.6
1.6
)
/
2
(1)
V _AC
−OFF
(RMS
)
=
(0.81×
R_HV + 1.6
1.6
)
/
2
(2)
Short-Circuit Protection (SCP)
This protection is used to handle the huge output
demand if the power supply output is suddenly shorted
to ground. If VDD drops under 10V and the sensed
voltage is higher than the limited threshold voltage, SCP
is triggered and PWM output is latched off. This latch
condition is reset only if VDD is discharged under 4V or
by unplugging AC power line.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16.5V and 9V, respectively. During startup, the hold-up
capacitor must be charged to 16.5V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply VDD before the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 9V during startup. This UVLO
hysteresis window ensures that the hold-up capacitor is
adequate to supply VDD during startup.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and can not switch
off the gate driver.
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
13.5V Zener diode to protect power MOSFET
transistors against undesirable gate over voltage. A soft
driving waveform is implemented to minimize EMI.
V_DD Over-Voltage Protection (OVP)
VDD over-voltage protection is built in to prevent damage
due to abnormal conditions. If the VDD voltage is over
the over-voltage protection voltage (VDD-OVP) and lasts
for tD-OVP, the PWM pulses are disabled until the VDD
voltage drops below 4V, then restarts again.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 8ms soft-start
circuit significantly reduces the startup current spike and
output voltage overshoot.
© 2009 Fairchild Semiconductor Corporation
FAN6747 • Rev. 1.0.1
12
www.fairchildsemi.com