NM24C04U Datasheet, PDF (11/13 Pages) Fairchild Semiconductor – EEPROM 2-Wire Bus Interface

Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
address is set to a one. There are three basic read operations:
current address read, random read, and sequential read.
Current Address Read
Internally the NM24C04U/05U contains an address counter that
maintains the address of the last byte accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n + 1. Upon receipt of the slave address with R/W set to
one, the NM24C04U/05U issues an acknowledge and transmits
the eight bit byte. The master will not acknowledge the transfer
but does generate a stop condition, and therefore the NM24C04U/
05U discontinues transmission. Refer to Figure 8 for the se-
quence of address, acknowledge and data transfer.
Random Read
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address and then the byte address it is to read. After the
byte address acknowledge, the master immediately reissues the
start condition and the slave address with the R/W bit set to one.
This will be followed by an acknowledge from the NM24C04U/05U
and then by the eight bit data. The master will not acknowledge the
transfer but does generate the stop condition, and therefore the
NM24C04U/05U discontinues transmission. Refer to Figure 9 for
the address, acknowledge and data transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24C04U/05U continues to output data for each
acknowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter "rolls over" and the
NM24C04U/05U continues to output data for each acknowledge
received. Refer to Figure 10 for the address, acknowledge, and
data transfer sequence.
Current Address Read (Figure 8)
S
T
S
Bus Activity: A
SLAVE
T
Master
R ADDRESS
O
T
P
SDA Line
Bus Activity:
NM24C04U/05U
Random Read (Figure 9)
S
T
Bus Activity: ^A
Master
R
T
SLAVE
ADDRESS
A
NO
C
DATA
A
K
C
K
DS800008-17
WORD
ADDRESS
S
T
A
SLAVE
R
ADDRESS
T
SDA Line
Bus Activity:
NM24C04U/05U
A
A
C
C
K
K
A
C
DATA n
K
S
T
O
P
NO
A
C
K
DS800008-18
Sequential Read (Figure 10)
Bus Activity:
Master
Slave
Address
SDA Line
A
Bus Activity:
C
NM24C04U/05U
K
DATA n +1
A
A
A
C
C
C
K
K
K
DATA n +1
DATA n + 2
S
T
O
P
DATA n + x
NO
A
C
K
DS800008-19
11
NM24C04U/NM24C05U Rev. C.1
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