ML4804 Datasheet, PDF (11/14 Pages) Fairchild Semiconductor – Power Factor Correction and PWM Controller Combo

FUNCTIONAL DESCRIPTION (Continued)
No voltage error amplifier is included in the PWM stage of
the ML4804, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate
the design of optocoupler feedback circuitry, an offset has
been built into the PWM’s RAMP 2 input which allows
V_DC to command a zero percent duty cycle for input
voltages below 1.25V.
PWM Current Limit
The DC I_LIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.
V_IN OK Comparator
The V_IN OK comparator monitors the DC output of the
PFC and inhibits the PWM if this voltage on V_FB is less
than its nominal 2.45V. Once this voltage reaches 2.45V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start begins.
PWM Control (RAMP 2)
When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (R_RAMP2, C_RAMP2), that will have a
minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
ML4804
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and start-
up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:
C_SS
=
t _DELAY
×
25µA
1.25V
(6)
where C_SS is the required soft start capacitance, and
t_DELAY is the desired start-up delay.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
Solving for the minimum value of C_SS:
C_SS
=
5ms
×
25µA
1.25V
= 100nF
(6a)
Caution should be exercised when using this minimum
soft start capacitance value because premature charging of
the SS capacitor and activation of the PWM section can
result if V_FB is in the hysteresis band of the V_IN OK
comparator at start-up. The magnitude of V_FB at start-up is
related both to line voltage and nominal PFC output
voltage. Typically, a 1.0µF soft start capacitor will allow
time for V_FB and PFC out to reach their nominal values
prior to activation of the PWM section at line voltages
between 90Vrms and 265Vrms.
L1
I1
+
VIN
DC
SW2 I2 I3
I4
SW1
RL
C1
RAMP
REF _+–EAU3
RAMP
OSC
CLK
U4
+
– _U1
DFF
RQ
D ^U2
Q
CLK
VEAO
VSW1
TIME
TIME
Figure 4. Typical Trailing Edge Control Scheme
REV. 1.0.2 3/9/2001
11