FAN5230 Datasheet, PDF (11/16 Pages) Fairchild Semiconductor – System Electronics Regulator for Mobile PCs

FAN5230
3.3V and 5V Under-voltage Protection
When the output voltage of either the 3.3V or 5V falls
below 75% of the nominal value, both converters, go into
under-voltage (UV) protection, after a 2µsec delay. In under-
voltage protection, the high and low side MOSFETs are
turned off. Once under-voltage protection is triggered, it
remains on until power is recycled or the SDWN pin is reset.
12V Architecture
The 12V converter is a traditional non-isolated fly-back (also
known as a "boost" converter). The converter’s input voltage
is the +5V switcher output, so that +12V can only be present
if +5V is present. Also, if the external MOSFET is off, the
output of the +12V converter is +5V, not zero. This in turn
will provide non-zero output for the 12V regulator.
For complete turn-off of the 12V regulator an external
P-channel MOSFET or an LDO regulator with on/off control
may be used. If an LDO is used for 12V then the boost
converter should be set to 13.2V using the external resistor
divider network. If the 12V “boost” converter is not used,
connect VFB12 (pin 15) to 5V-ALWAYS (pin 6).
12V Loop Compensation
The 12V converter should be run in discontinuous conduc-
tion mode. In this mode, the converter will be stable if a
capacitor with suitable ESR value is selected. A 68uF
tantalum with 500mA ripple current rating and 95mΩ is
recommended here.
12V Protection
The 12V converter is protected against overvoltage. If the
12V feedback is more than 10–15% above the nominal set
voltage, a comparator forces the MOSFET off until the volt-
age falls below the comparator threshold.
The 12V converter is also protected against over-current. If a
short circuit pulls the output below 9V, all of the switching
converters go into UV protection, after a 2µs delay. In UV
protection, all MOSFETs are turned off. Once UV protection
is triggered, it remains on until the input power is recycled or
the SDWN is reset.
5V/3.3V-ALWAYS Operation
The 5V-ALWAYS supply is generated from either the
on-chip linear regulator or through an internal switch from
the VFB pin of the 5V switching supply. The 5V-ALWAYS
supply should be decoupled to ground with a 10µF capacitor.
When the 5V switching supply is off, or if its output voltage
is not within tolerance, the 5V-ALWAYS switch is open, and
the linear regulator is on. When the 5V switching supply is
running and has an output voltage within specification, the
linear regulator is off, and the switch is on. The switch has
sufficiently low resistance that at maximum current draw on
the 5V-ALWAYS supply, the output voltage is regulated
within specifications.
The 3.3V-ALWAYS is generated from a linear regulator
attached internally to the 5V-ALWAYS. The 3.3V-ALWAYS
supply should be decoupled to ground with a 10µF capacitor.
The purpose of the two ALWAYS supplies (combined cur-
rent is specified to never exceed 50mA) is to provide power
to the system micro-controller (8051 class) as well as other
IC’s needing a stand-by power. The micro-controller as well
as the other IC’s could be operated from either 5V or 3.3V
ALWAYS, so the FAN5230 provides both.
5V/3.3V-ALWAYS Protections
The two internal linear regulators are current limited and
under-voltage protected. Once protection is triggered all
outputs are turned off until power is cycled or the SDWN is
reset.
Power good
Power good is asserted when both PWM Buck converters are
above specified threshold. No other regulators are monitored
by Power good. When PGOOD goes low it will stay low for
at least 10µsec (Tw). See fig. 5.
Vmain
Vth
12V Softstart and Sequencing
The 12V output is started at the same time as the 5V output.
The softly rising 5V output automatically generates a softly
rising 12V output. The duty cycle of the 12V PWM is lim-
ited to prevent excessive current draw.
The 12V supply must build up a voltage higher than the
UVLO limit (9V) by the time the 5V is above its UVLO
(3.75V) in order to avoid triggering of UV protection during
soft start.
PGOOD
t
t
Tw
Figure 5. PGOOD Timing Diagram
REV. 2.8.5 10/17/01
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