ML4826 Datasheet, PDF (10/16 Pages) Fairchild Semiconductor – PFC and Dual Output PWM Controller Combo

ML4826
PRODUCT SPECIFICATION
current transformer in the primary of the output stage, and is
thereby representative of the current flowing in the con-
verter’s output stage. DC ILIMIT, which provides cycle-by-
cycle current limiting, is typically connected to RAMP 2 in
such applications. For voltage-mode operation or certain
specialized applications, RAMP2 can be connected to a sep-
arate RC timing network to generate a voltage ramp against
which VDC will be compared. Under these conditions, the
use of voltage feedforward from the PFC buss can assist in
line regulation accuracy and response. As in current mode
operation, the DC ILIMIT input would be used for output
stage overcurrent protection.
No voltage error amplifier is included in the PWM stage of
the ML4826, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate
the design of optocoupler feedback circuitry, an offset has
been built into the PWM’s RAMP2 input which allows VDC
to command a zero percent duty cycle for input voltages
below 1.5V.
PWM Current Limit
The DC ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input volt-
age at this pin ever exceed 1V, the output of the PWM will be
disabled until the output flip-flop is reset by the clock pulse
at the start of the next PWM power cycle.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the PFC
and inhibits the PWM if this voltage on VFB is less than its
nominal 2.5V. Once this voltage reaches 2.5V, which corre-
sponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start commences.
RAMP2
The RAMP2 input is compared to the feedback voltage
(VDC) to set the PWM pulse width. In voltage mode it can
be generated using the same method used for the RTCT
input. In current mode the primary current sense and slope
compensation are fed into the RAMP2 input.
Peak current mode control with duty cycles greater than 50%
requires slope compensation for stability. Figure 4 displays
the method used for the required slope compensation. The
example shown adds the slope compensation signal to the
current sense signal. Alternatively, the slope compensation
signal can also be subtracted form the feedback signal
(VDC).
In setting up the slope compensation first determine the
down slope in the output inductor current. To determine the
actual signal required at the RAMP2 input, reflect 1/2 of the
inductor downslope through the main transformer, current
sense transformer to the ramp input.
Internal to the IC is a 1.5V offset in series with the RAMP2
input. In the example show the positive input to the PWM
comparator is developed from VREF (7.5V), this limits the
RAMP2 input (current sense and slope compensation) to 6
Volts peak. The composite waveform feeding the RAMP2
pin for the PWM consists of the reflected output current
signal along with the transformer magnetizing current and
the slope compensation signal.
Equation 8 describes the composite signal feeding RAMP2,
consisting of the primary current of the main transformer and
the slope compensation. Equation 9 solves for the required
slope compensation peak voltage.
V_RAMP2
=
^IPRI
+
12_--
×
-^V----^O-_L---^U---^T--
×
N^-N----SS--
×
T_S



×
n^----1_C^----_T^-
≤
V_FB
–
1.5V
(8)
(9) VSC=



12_--
×
V_{-----O---L--U-----T--}
×
NN_-----SP--
×
TS



×
R_{-----S---n--E-C---N--T---S----E---}
=
12_--
× -₂--⁴-₀--⁸--_µ--^V--_H--
× ¹⁹----⁴⁰--
× 5µ sec ⁴---₂-⁷--₀-¹---₀-^Ω---
=
2.2 V
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.5V. Start-up delay can be programmed by
the following equation:
C_SS = t_DELAY × ⁵--₁--⁰-_.--₅-^µ--_V-^A---
(10)
where CSS is the required soft start capacitance, and tDELAY
is the desired start-up delay.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at least
5ms.
Solving for the minimum value of CSS:
C_SS = 5ms × ⁵--₁--⁰-_.--₅-^µ--_V-^A--- = 167nF
(11)
Caution should be exercised when using this minimum soft
start capacitance value because premature charging of the SS
capacitor and activation of the PWM section can result if
VFB is in the hysteresis band of the VIN OK comparator at
start-up. The magnitude of VFB at start-up is related both to
line voltage and nominal PFC output voltage. Typically, a
1.0µF soft start capacitor will allow time for VFB and PFC
out to reach their nominal values prior to activation of the
PWM section at line voltages between 90Vrms and
265Vrms.
V_CC
The ML4826 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the voltage
internal to the part at 13.5V. This allows a low power dissi-
pation while at the same time delivering 10V of gate drive at
the PWM OUT and PFC OUT outputs. It is important to
limit the current through the part to avoid overheating or
destroying the part.
10
REV. 1.0.5 2/14/02