ISL9N307AP3 Datasheet, PDF (10/11 Pages) Fairchild Semiconductor – N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs

SPICE Thermal Model
REV May 2001
ISL9N307AP3T
CTHERM1 th 6 2.4e-3
CTHERM2 6 5 4.8e-3
CTHERM3 5 4 6.9e-3
CTHERM4 4 3 7e-3
CTHERM5 3 2 7.4e-3
CTHERM6 2 tl 2.4e-2
RTHERM1 th 6 4.6e-3
RTHERM2 6 5 1e-2
RTHERM3 5 4 3.4e-2
RTHERM4 4 3 2.2e-1
RTHERM5 3 2 3e-1
RTHERM6 2 tl 5.1e-1
SABER Thermal Model
SABER thermal model ISL9N307AP3T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.4e-3
ctherm.ctherm2 6 5 = 4.8e-3
ctherm.ctherm3 5 4 = 6.9e-3
ctherm.ctherm4 4 3 = 7e-3
ctherm.ctherm5 3 2 = 7.4e-3
ctherm.ctherm6 2 tl = 2.4e-2
rtherm.rtherm1 th 6 = 4.6e-3
rtherm.rtherm2 6 5 = 1e-2
rtherm.rtherm3 5 4 = 3.4e-2
rtherm.rtherm4 4 3 = 2.2e-1
rtherm.rtherm5 3 2 = 3e-1
rtherm.rtherm6 2 tl = 5.1e-1
}
th
JUNCTION
RTHERM1
6
RTHERM2
5
RTHERM3
4
RTHERM4
3
RTHERM5
2
RTHERM6
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
tl
CASE
©2002 Fairchild Semiconductor Corporation
Rev. B, January 2002