FAN5063 Datasheet, PDF (10/14 Pages) Fairchild Semiconductor – ACPI Dual Switch Controller

FAN5063
PRODUCT SPECIFICATION
300
200
ESR (mΩ)
100
47 100
200
C (µF)
300 330 400
Figure 6. Recommended C vs. ESR for
Stable Operation of the 3.3V Dual
Adjustable Dual Output
The adjustable dual output is intended to provide power to
RAMBUS or SDRAM memory.
Adjustable dual is generated by one external NPN bipolar
acting as a linear regulator from +5V main, and one linear
regulator internal to the FAN5063 from +5V standby, as
shown in Figure 4, and in the block diagram on the front
page. When main power is present, the NPN Q3 linear regu-
lates, and when main power is absent, the internal linear reg-
ulator is on. Q3 cannot be substituted with a MOSFET. If
used in one direction, the MOSFET’s body diode would per-
mit back-feed; if used in the other direction, it would short-
circuit the linear regulator action.
The state of the external MOSFET and the internal linear
regulator is controlled by the SLP_S3 and PWROK lines,
and additionally the SLP_S5 line, as shown in Figure 3.
When SLP_S5 is de-asserted, both the external MOSFET
and the internal linear regulator are off, and there is no out-
put voltage on the 3.3V SDRAM line.
If the SLP_S5 line is asserted, the adjustable dual output is
on. In this condition, if either the SLP_S3 or the PWROK
line, or both, are de-asserted, the linear regulator is on and
the MOSFET is off. Only in the case if both the SLP_S3 and
the PWROK lines are asserted, the MOSFET is on and the
linear regulator is off.
In a typical system, it is anticipated that standby current will
be a maximum of 144mA, and full-power current may be as
high as 2A. This places some significant constraints on the
selection of Q3. Since its input may be as low as (5V – 5%)
= 4.75V, there is only 4.75V – 3.3V = 1.45mV of V_CE head-
room for its operation as a linear regulator. For this reason
the FAN5063 can provide up to 200mA of steady-state base
current. The TIP41A device shown has a sufficiently low V_CE,
sat ^{to guarantee worst-case regulation even at 2A I}E ^{with this}
base current.
The output voltage of the Adjustable Dual is set with two
resistors as shown in Figure 4, according to the equation.
Vadj
=
1.25
V
•
-^R----¹----⁺----^R-----²
R₂
10
FAN5063 ACPI Control Lines
As already discussed, the FAN5063 outputs are controlled
by the three ACPI control lines, SLP_S3, SLP_S5 and
PWROK, as summarized in Tables 1 and 2. System design-
ers must in particular be careful to ensure that their system is
designed with SLP_S5, not SLP_S5; if SLP_S5 is used, it
must be inverted before being used with the FAN5063.
The control lines have internal pull-ups of approximately
40µA, and so can be controlled by open collector drivers if
desired. In a noisy system, it may be desirable to filter these
lines, which can be done with a 1KΩ resistor and a small
capacitor.
FAN5063 Dynamic Operation
The FAN5063 is designed to minimize the output capaci-
tance required to hold up the various output lines during
transitions between different states. Thus in particular, the
adjustable dual output has guaranteed minimum overlap
time, the time (as shown in Figure 2) during a state transition
during which both main and standby are connected to the
output. This overlap time guarantees that a power source is
always connected to the output, so that there will be no dip in
the output voltage during state transitions. There is also a
maximum overlap time, to ensure that the standby power
doesn’t have to source main power very long, thus minimiz-
ing thermal stress on the standby device.
The 3.3V dual is different because it is powered by both a
linear regulator and a switch. If the linear regulator were to
turn on while the switch is on (or vice versa) the linear regu-
lator would supply power to the main line through the
switch. For this reason, the linear regulator must be off
before the switch is on, and vice versa. Thus, this output has
guaranteed minimum deadtime when both linear regulator
and switch are off. During this time, the output capacitor
must hold up the load, and so there is also a specified maxi-
mum deadtime, allowing a maximum necessary capacitance
to be selected, see below.
Stability
As with all linear regulators, the FAN5063’s linear regulators
require a minimum load. With the exception of the 3.3V dual
output, however, all of these minimum loads are internal to
the FAN5063. The 3.3V dual output requires a minimum load
of 50mA; if a situation may occur in which the load is less than
50mA, additional steps may be necessary to ensure stability.
Furthermore, depending on location, it may be necessary to
bypass the drain (or collector) of the linear regulator with a
low ESR capacitor for stability. As a rule of thumb, if the
pass element is more than 1” from its power source, it should
have a bypass.
REV. 1.0.0 12/4/00