TMC2302A Datasheet, PDF (1/36 Pages) Fairchild Semiconductor – Image Manipulation Sequencer

TMC2302A
Image Manipulation Sequencer
40 MHz
www.fairchildsemi.com
Features
• Asynchronous loading of control parameters
• Rapid (25ns per pixel) rotation, warping, panning, and
scaling of images
• Three-dimensional image addressing capability
• General third-order polynomial transformations in two
dimensions on-chip
• Three-dimensional transformation of up to order 1.5 also
supported
• Flexible, user-configurable pixel datapath timing structure
• Static convolutional filtering of up to 16 x 16 Pixel (one-
pass), 256 x 256 pixel (two-pass) or 256 x 256 x 256 pixel
(three-pass) windows
• User-selectable source image subpixel resolution of
2^-8 to 2^-16
• Pin-compatible upgrade to TMC2302
• 24-bit (optional 36-bit) positioning precision within the
source image space, 48-bit internal precision
• Low power CMOS process
• Available in a 120-pin Plastic Pin Grid Array and 120-lead
Metric Quad Flat Pack
Applications
• High-performance video special-effects generators
• Guidance systems
• Image recognition
• Robotics
• High-precision image registration
Description
The TMC2302A, a pin-compatible replacement for the
TMC2302, is a high-speed self-sequencing address genera-
tor which supports image manipulations such as rotation,
rescaling, warping, filtering, and resampling. It remaps the
pixel locations of a target (display) space back into those of a
source image space. The degree and type of image manipula-
tion is determined by the remapping selected.
To remap from the target to the source space, this integrated
circuit computes a series of polynomials of the target space
coordinates, based on user-assigned coefficients. Two
TMC2302A chips can generate third-order warps of a two-
dimensional image, whereas three can second-order warp a
three-dimensional image.
Simplified Block Diagram
IDAT15-0
ASYNCHRONOUS ^IADR6-0
HOST INTERFACE _ICS
IWR
SYNC
SYNCHRONOUS
HOST INTERFACE
NOOP
INIT
CLK
CONTROL
PARAMETER
REGISTERS
CONTROL
SOURCE
ADDRESS
GENERATOR
WALK
COUNTER
TARGET
ADDRESS
GENERATOR
65-2302-01
OES
SOURCE MEMORY
SADR23-0
INTERFACE
SVAL
OEK
KADR7-0
ACC
TWR
CONVOLUTIONAL
CONTROL
OET
TADR11-0
TVAL
TARGET
MEMORY
INTERFACE
END
DONE
SYNC FLAGS
Rev. 0.9.2