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TMC2242A Datasheet, PDF (1/16 Pages) Fairchild Semiconductor – Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz | |||
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www.fairchildsemi.com
TMC2242A/TMC2242B
Digital Half-Band Interpolating/Decimating Filter
12-bit In/16-bit Out, 60 MHz
Features
⢠TMC2242A and TMC2242B are pin-compatible with
TMC2242
⢠User selectable interpolate gain, -6 dB or 0 dB (2242B)
⢠30, 40 and 60 MHz speed grades
⢠User selectable 2:1 decimation, 1:2 interpolation, and
equal-rate ï¬lter modes
⢠Passband ripple < ±0.01 dB
⢠Stopband rejection 59.4 dB from 0.28 to 0.50 x fs
⢠Cascading two TMC2242A or TMC2242B meets
CCIR 601 low-pass ï¬lter requirement
⢠Dedicated 12-bit 2's complement input data port and
16-bit output data port with user-selectable rounding from
9 to 16 bits
⢠Two's complement or offset binary output format
⢠Built-in limiter prevents overï¬ow
⢠Single +5 Volt power supply operation
⢠Small 44-Lead PLCC and 44-Lead MQFP
Applications
⢠Low-cost video ï¬ltering
⢠Chrominance bandwidth limiter
⢠Simple, inexpensive video D/A post-ï¬lters
⢠Reduced cost and complexity for A/D anti-aliasing ï¬lters
⢠High-performance digital low-pass ï¬lters
⢠Digital waveform reconstruction post-ï¬ltering
⢠Telecommunications
⢠Direct digital synthesis
⢠Radar
Description
The TMC2242A and TMC2242B are ï¬xed-coefï¬cient lin-
ear-phase half-band (low-pass) digital ï¬lters. They can be
used to halve or double the sampling rate of a digital signal.
When used as a decimating post-ï¬lter with a double-speed
oversampling A/D converter, they greatly reduce the cost and
complexity of anti-aliasing ï¬lters required ahead of the A/D
converter. When used as an interpolating pre-ï¬lter with a
double-speed oversampling D/A converter, the TMC2242A
and TMC2242B signiï¬cantly reduce the design complexity
and production cost of reconstruction ï¬lters used on D/A
outputs.
The TMC2242A and TMC2242B user selects the mode of
operation (decimate, interpolate, or equal-rate) and round-
ing. The TMC2242A and TMC2242B accept 12-bit 2's com-
plement data at up to 60 MHz and output saturated
(overï¬ow-protected) 2's complement or offset binary data
rounded to from 9 to 16 bits. Within the speed grade I/O
limit, the output sample rate may be 1/2, 1, or 2 times the
input sample rate.
Block Diagram
12
12
SI11-0
CLK
DEC
INT
SYNC
Control
12
12 55 Tap
FIR
Filter
Round 16
16
and
Limit
Interpolate 0-1-0-1
Decimate, Equal Rate 1-1-1-1
3
OE
16
SO15-0
TCO
RND2-0
65-2242A-01
Rev. 1.2.0
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