TMC22071A Datasheet, PDF (1/24 Pages) Fairchild Semiconductor – Genlocking Video Digitizer

TMC22071A
Genlocking Video Digitizer
www.fairchildsemi.com
Features
• Fully integrated acquisition
• 3-channel video input multiplexer
• Two-stage video clamp
• Automatic gain adjustment
• Sync detection and separation
• Pixel and subpixel adjustment of HSYNC-to-Video
timing
• Genlock to NTSC or PAL inputs
• Clock generation
• 8-bit video A/D converter
• Microprocessor interface
• Line-locked pixel rates
- 12.27 MHz NTSC
- 13.5 MHz NTSC or PAL
• Direct interface to TMC22x9x encoders
• Built-in circuitry for crystal oscillator
• No tuning or external voltage reference required
• 68 Lead PLCC or 100 Lead MQFP package
Applications
• Frame grabber
• Digital VCR/VTR
• Desktop video
Description
The TMC22071A Genlocking Video Digitizer converts stan-
dard baseband composite NTSC or PAL video into 8-bit dig-
ital composite video data. It extracts horizontal and vertical
sync signals and generates a pixel clock for the on-board
8-bit A/D converter and a 2x clock for the transfer of data to
subsequent video processing decoding or encoding with the
TMC22x5y Video Decoder or TMC22x9x Digital Video
Encoder family. It also measures the color subcarrier phase
and frequency and provides this data to the Encoder (for gen-
locked color NTSC or PAL encoding), or a frame buffer (for
frame capture) over the digital composite video port.
The TMC22071A includes a three-channel video input mul-
tiplexer, analog clamp, variable gain amplifier, and digital
back porch clamp. The on-board oscillator circuitry gener-
ates the clock from a 20 MHz crystal or the clock source may
be an external oscillator. It is programmable over a micro-
processor interface for NTSC or PAL operation. No external
component changes and no production tuning or service
adjustments are ever required.
The TMC22071A is fabricated in an advanced CMOS
process, and is packaged in a 68 Lead PLCC or 100 Lead
MQFP. Its performance is guaranteed from 0°C to 70°C.
Block Diagram
VIN1
VIN2
VIN3
ANALOG
CLAMP
GAIN
A/D
CONTROL
D/A
D/A
+1.2V
MICROPROCESSOR
INTERFACE
ANALOG INTERFACE
BACK PORCH
CLAMP
LOWPASS
FILTER
DIRECT
DIGITAL
SYNTHESIZER
DATA
SELECTOR
CVBS7-0
SUBCARRIER
PHASE-LOCKED
LOOP
SYNC
SEPARATOR
GVSYNC
GHSYNC
HORIZONTAL
PHASE-LOCKED
LOOP
PXCK
LDV
VALID
DDS/PIXEL CLOCK INTERFACE
65-22071-01
Rev. 1.0.5