SSW4N60B Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – 600V N-Channel MOSFET

November 2001
SSW4N60B / SSI4N60B
600V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supplies.
Features
• 4.0A, 600V, R_DS(on) = 2.5Ω @V_GS = 10 V
• Low gate charge ( typical 22 nC)
• Low Crss ( typical 14 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
D
GS
D²-PAK
SSW Series
GDS
I²-PAK
SSI Series
G!
D
!
!
#"
!
!
!
S
Absolute Maximum Ratings T_C = 25°C unless otherwise noted
Symbol
V_DSS
I_D
I_DM
V_GSS
E_AS
I_AR
E_AR
dv/dt
P_D
T_J, T_stg
T_L
Parameter
Drain-Source Voltage
Drain Current
- Continuous (T_C = 25°C)
- Continuous (T_C = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (T_A = 25°C) *
Power Dissipation (T_C = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8! from case for 5 seconds
SSW4N60B / SSI4N60B
600
4.0
2.5
16
± 30
240
4.0
10
5.5
3.13
100
0.8
-55 to +150
300
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Thermal Characteristics
Symbol
Parameter
R_θJC
Thermal Resistance, Junction-to-Case
R_θJA
Thermal Resistance, Junction-to-Ambient *
R_θJA
Thermal Resistance, Junction-to-Ambient
* When mounted on the minimum pad size recommended (PCB Mount)
Typ
Max
Units
--
1.25
°C/W
--
40
°C/W
--
62.5
°C/W
©2001 Fairchild Semiconductor Corporation
Rev. B, November 2001