SSTV16857 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – 14-Bit Register with SSTL-2 Compatible I/O and Reset

September 2000
Revised June 2005
SSTV16857 • SSTVN16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin PC1600, 2100, and 2700 DDR DIMM
applications. The SSTVN16857 is a 14-bit register
designed for use with 184 and 232 pin PC3200 DDR DIMM
applications. These devices have a differential input clock,
SSTL-2 compatible data inputs and a LVCMOS compatible
RESET input. These devices have been designed for com-
pliance with the JEDEC DDR module and register specifi-
cations.
The devices are fabricated on an advanced submicron
CMOS process and are designed to operate at power sup-
plies of less than 3.6V’s.
Features
s Compliant with DDR-I registered module specifications
s Operates at 2.5V r 0.2V V_DD
s SSTL-2 compatible input and output structure
s Differential SSTL-2 compatible clock inputs
s Low power mode when device is reset
s Industry standard 48 pin TSSOP package
Ordering Code:
Order Number Package Number
Package Description
SSTV16857MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
SSTVN16857MTD
(Preliminary)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
Q₁-Q₁₄
D₁-D₁₄
RESET
CK
Description
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
CK
V_REF
V_DDQ
V_DD
Negative Master Clock Input
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
Truth Table
RESET
D_n
CK
CK
Q_n
L
X or
X or
X or
L
Floating Floating Floating
H
L
n
p
L
H
H
n
p
H
H
X
L
H
Q_n
H
X
H
L
Q_n
L Logic LOW
H Logic HIGH
X Don’t Care, but not floating unless noted
n LOW-to-HIGH Clock Transition
p HIGH-to-LOW Clock Transition
© 2005 Fairchild Semiconductor Corporation DS500387
www.fairchildsemi.com