SSN1N45B Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – 450V N-Channel MOSFET

SSN1N45B
450V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for electronic ballasts based on half bridge
configuration.
Features
• 0.5A, 450V, R_DS(on) = 4.25Ω @V_GS = 10 V
• Low gate charge ( typical 6.5 nC)
• Low Crss ( typical 6.5 pF)
• 100% avalanche tested
• Improved dv/dt capability
• Gate-Source Voltage ± 50V guaranteed
D
!
GDS
TO-92
SSN Series
G!
●
◀▲
●
●
!
S
Absolute Maximum Ratings T_C = 25°C unless otherwise noted
Symbol
V_DSS
I_D
I_DM
V_GSS
E_AS
I_AR
E_AR
dv/dt
P_D
T_J, T_stg
T_L
Parameter
Drain-Source Voltage
Drain Current
- Continuous (T_C = 25°C)
- Continuous (T_C = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (T_A = 25°C)
Power Dissipation (T_L = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
SSN1N45B
450
0.5
0.32
4.0
± 50
108
0.5
0.25
5.5
0.9
2.5
0.02
-55 to +150
300
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Thermal Characteristics
Symbol
Parameter
Typ
R_θJL
Thermal Resistance, Junction-to-Lead
(Note 6a)
--
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 6b)
--
Max
Units
50
°C/W
140
°C/W
©2002 Fairchild Semiconductor Corporation
Rev. A, November 2002