SG6516_08 Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – PC Power Supply Supervisors

April 2008
SG6516
PC Power Supply Supervisors
Features
ƒ Two 12V Sense Input Pins: VS12 and VS12B
ƒ Over-Voltage Protection (OVP) for 3.3V, 5V,
and two 12V
ƒ Over-Current Protection (OCP) for 3.3V, 5V,
and two 12V
ƒ Under-Voltage Protection (UVP) for 3.3V, 5V,
and two 12V
ƒ Open-Drain Output for PGO and FPO Pins
ƒ 300ms Power-Good Delay
ƒ 2.8ms PSON Control to FPO Turn-off Delay
ƒ 48ms PSON Control Delay
ƒ No Lock-up During the Fast AC Power On/Off
ƒ Wide Supply Voltage Range: 4V to 15V
Applications
ƒ Switch-Mode Power Supplies with Active PFC
ƒ Servo System Power Supplies
ƒ PC-ATX Power Supplies
Description
The SG6516 is designed to provide the supply voltage,
current supervisor, remote on/off (PSON), power good
(PGO) indicator, and fault protection (FPO) functions for
switching power systems.
For supervisory functions, it provides the over-voltage
protection (OVP) for 3.3V, 5V, and two 12V; over-
current protection (OCP) for 3.3V, 5V, and two 12V;
under-voltage protection (UVP) for 3.3V, 5V, and two
12V. When 3.3V, 5V, or 12V voltage decreases to 2.3V,
3.5V, and 9V, respectively, the under-voltage protection
function is enabled. FPO is set HIGH to turn off the
PWM controller IC. The voltage difference across
external current shunt is used for OCP functions. An
external resistor can be used to adjust the protection
threshold. An additional protection input pin provides
the flexibility for designing protection circuits.
The power supply is turned on after a 48ms delay when
PSON signal is set from HIGH to LOW. To turn off the
power supply, the PSON signal is set from LOW to
HIGH with a delay of 48ms. The PGI circuitry provides a
power-down warning signal for PGO. When PGI input is
lower than the internal 1.25V reference voltage, the
PGO signal is pulled LOW.
Ordering Information
Part Number Operating Temperature Range
Package
SG6516DZ
SG6516SZ
-40°C to +85°C
-40°C to +85°C
16-pin Dual In-Line Package (DIP)
16-pin Small Outline Package (SOP)
All packages are lead free per JEDEC: J-STD-020B standard.
Packing
Method
Rail
Tape & Reel
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com