SCAN18373T Datasheet, PDF (1/12 Pages) National Semiconductor (TI) – Transparent Latch with TRI-STATE Outputs

October 1991
Revised May 2000
SCAN18373T
Transparent Latch with 3-STATE Outputs
General Description
The SCAN18373T is a high speed, low-power transparent
latch featuring separate data inputs organized into dual 9-
bit bytes with byte-oriented latch enable and output enable
control signals. This device is compliant with IEEE 1149.1
Standard Test Access Port and Boundary Scan Architec-
ture with the incorporation of the defined boundary-scan
test logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and
Test Clock (TCK).
Features
s IEEE 1149.1 (JTAG) Compliant
s Buffered active-low latch enable
s 3-STATE outputs for bus-oriented applications
s 9-bit data busses for parity applications
s Reduced-swing outputs source 32 mA/sink 64 mA
s Guaranteed to drive 50Ω transmission line to TTL input
levels of 0.8V and 2.0V
s TTL compatible inputs
s 25 mil pitch SSOP (Shrink Small Outline Package)
s Includes CLAMP and HIGHZ instructions
s Member of Fairchild’s SCAN Products
Ordering Code:
Order Number Package Number
Package Description
SCAN1837TSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
AI_(0–8), BI_(0–8)
ALE, BLE
AOE₁, BOE₁
AO_(0–8), BO_(0–8)
Description
Data Inputs
Latch Enable Inputs
3-STATE Output Enable Inputs
3-STATE Latch Outputs
Truth Tables
ALE
X
H
H
L
Inputs
AOE₁
H
L
L
L
AI_(0–8)
X
L
H
X
Inputs
BLE
BOE₁
BI_(0–8)
X
H
X
H
L
L
H
L
H
L
L
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
AO₀ = Previous AO before H-to-L transition of ALE
BO₀ = Previous BO before H-to-L transition of BLE
AO_(0–8)
Z
L
H
AO₀
BO_(0–8)
Z
L
H
BO₀
© 2000 Fairchild Semiconductor Corporation DS010962
www.fairchildsemi.com