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RMPA1963 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – US-PCS CDMA, CDMA2000-1X and WCDMA Power Amplifier Module | |||
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PRELIMINARY
May 2005
RMPA1963 i-Loâ¢
i-L
US-PCS CDMA, CDMA2000-1X and WCDMA
o
â¢
Power Amplifier Module
Features
â 38% CDMA/WCDMA efficiency at +28 dBm Pout
â 14% CDMA/WCDMA efficiency (85 mA total current) at
+16 dBm Pout
â Meets HSDPA performance requirements
â Linear operation in low-power mode up to +19 dBm
â Low quiescent current (Iccq): 25 mA in low-power mode
â Single positive-supply operation with low power and shut-
down modes
⢠3.4V typical Vcc operation
⢠Low Vref (2.85V) compatible with advanced handset
chipsets
â Compact Lead-free compliant LCC package â
(4.0 X 4.0 x 1.5 mm nominal)
â Industry standard pinout
â Internally matched to 50 Ohms and DC blocked RF
input/output
â Meets IS-95/CDMA2000-1XRTT/WCDMA performance
requirements
General Description
The RMPA1963 Power Amplifier Module (PAM) is Fairchildâs lat-
est innovation in 50 Ohm matched, surface mount modules tar-
geting US-PCS CDMA/WCDMA/HSDPA and Wireless Local
Loop (WLL) applications. Answering the call for ultra-low DC
power consumption and extended battery life in portable elec-
tronics, the RMPA1963 uses novel proprietary circuitry to dra-
matically reduce amplifier current at low to medium RF output
power levels (< +16 dBm), where the handset most often oper-
ates. A simple two-state Vmode control is all that is needed to
reduce operating current by more than 50% at 16 dBm output
power, and quiescent current (Iccq) by as much as 70% com-
pared to traditional power-saving methods. No additional cir-
cuitry, such as DC-to-DC converters, are required to achieve
this remarkable improvement in amplifier efficiency. Further, the
4x4x1.5 mm LCC package is pin-compatible and a drop-in
replacement for last generation 4x4 mm PAMs widely used
today, minimizing the design time to apply this performance-
enhancing technology. The multi-stage GaAs Microwave Mono-
lithic Integrated Circuit (MMIC) is manufactured using Fairchild
RFâs InGaP Heterojunction Bipolar Transistor (HBT) process.
Device
Functional Block Diagram
(Top View)
Vcc1 1
RF IN 2
GND 3
Vmode 4
Vref 5
MMIC
INPUT
MATCH
BIAS/MODE SWITCH
10 Vcc2
OUTPUT
MATCH
9 GND
8 RF OUT
7 GND
6 GND
11 (paddle ground on package bottom)
©2005 Fairchild Semiconductor Corporation
1
RMPA1963 i-Lo⢠Rev. H
www.fairchildsemi.com
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