RMPA0966 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – Cellular CDMA, CDMA2000-1X and WCDMA Power Amplifier Module

PRELIMINARY
November 2005
RMPA0966 i-Lo™
Cellular CDMA, CDMA2000-1X and WCDMA
Power Amplifier Module
Features
■ 42% CDMA/WCDMA efficiency at +28 dBm Pout
■ 21% CDMA/WCDMA efficiency (56 mA total current) at
+16 dBm Pout
■ Meets HSDPA performance requirements
■ 50% AMPS mode efficiency at +31 dBm Pout
■ Low quiescent current (Iccq): 15 mA in low-power mode
■ Single positive-supply operation with low power and
shutdown modes
• 3.4V typical Vcc operation
• Low Vref (2.85V) compatible with advanced handset
chipsets
■ Compact Lead-free compliant LCC package –
(4.0 X 4.0 x 1.0 mm nominal)
■ Industry standard pinout
■ Internally matched to 50 Ohms and DC blocked RF
input/output
■ Meets IS-95/CDMA2000-1XRTT/WCDMA performance
requirements
Device
General Description
The RMPA0966 Power Amplifier Module (PAM) is Fairchild’s lat-
est innovation in 50 Ohm matched, surface mount modules tar-
geting Cellular CDMA/WCDMA/HSDPA, AMPS and Wireless
Local Loop (WLL) applications. Answering the call for ultra-low
DC power consumption and extended battery life in portable
electronics, the RMPA0966 uses novel proprietary circuitry to
dramatically reduce amplifier current at low to medium RF out-
put power levels (<+16 dBm), where the handset most often
operates. A simple two-state Vmode control is all that is needed
to reduce operating current by more than 60% at 16 dBm output
power, and quiescent current (Iccq) by as much as 70% com-
pared to traditional power-saving methods. No additional cir-
cuitry, such as DC-to-DC converters, are required to achieve
this remarkable improvement in amplifier efficiency. Further, the
4x4x1.0 mm LCC package is pin-compatible and a drop-in
replacement for last generation 4x4 mm PAMs widely used
today, minimizing the design time to apply this performance-
enhancing technology. The multi-stage GaAs Microwave Mono-
lithic Integrated Circuit (MMIC) is manufactured using Fairchild
RF’s InGaP Heterojunction Bipolar Transistor (HBT) process.
Functional Block Diagram
Vref 1
Vmode 2
GND ³
RF IN ⁴
Vcc1 5
MMIC
(Top View)
BIAS/MODE SWITCH
INPUT
MATCH
10 GND
9 GND
OUTPUT
MATCH
8 RF OUT
7 GND
6 Vcc2
11 (paddle ground on package bottom)
©2005 Fairchild Semiconductor Corporation
1
RMPA0966 i-Lo™ Rev. A
www.fairchildsemi.com