NM34W02 Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect

March 1999
NM34W02
2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Designed with Permanent Write-Protection for First 128 Bytes for Serial Presence
Detect Application on Memory Modules (PC100 Compliant)
General Description
The NM34W02 is 2048 bits of CMOS non-volatile electrically
erasable memory. This device is specifically designed to support
Serial Presence Detect circuitry in memory modules. This com-
munications protocol uses CLOCK (SCL) and DATA I/O (SDA)
lines to synchronously clock data between the master (for ex-
ample a microprocessor) and the slave EEPROM device(s).
The contents of the non-volatile memory allows the CPU to
determine the capacity of the module and the electrical character-
istics of the memory devices it contains. This will enable "plug and
play" capability as the module is read and PC main memory
resources utilized through the memory controller.
The first 128 bytes of the memory of the NM34W02 can be
permanently Write Protected by writing to the "WRITE PROTECT"
Register. Write Protect implementation details are described
under the section titled Addressing the WP Register. In addition,
like the NM24Wxx product family, the entire memory array can be
write-protected through "WP" pin.
The NM34W02 is available in a JEDEC standard TSSOP package
for low profile memory modules for systems requiring efficient
space utilization such as in a notebook computer. Two options are
available: L - Low Voltage and LZ - Low Power, allowing the part
to be used in systems where battery life is of primary importance.
Features
s PC100 Compliant
s Extended Operating Voltage: 2.7V-5.5V
s Software Write-Protection for first 128 bytes
s Hardware Write-Protection for entire memory array
s 200 µA active current typical
– 1.0 µA standby current typical (L)
– 0.1 µA standby current typical (LZ)
s IIC compatible interface
– Provides bidirectional data transfer protocol
s Sixteen byte page write mode
– Minimizes total write time per byte
s Self timed write cycle
- Typical write cycle time of 6ms
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin TSSOP and 8-pin SO
s Temperature Ranges: Commercial and Extended
Block Diagram
VCC
VSS
WP
SDA
SCL
A2
A1
A0
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &CONTROL
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
16
XDEC
E2PROM
ARRAY
16 x 16 x 8
0/1/2/3
4
4
16
YDEC
Write Protect
Register
Device Address Bits
DIN
8
CK
DATA REGISTER
DOUT
© 1999 Fairchild Semiconductor Corporation
1
NM34W02 Rev. C.2
DS500078-1
www.fairchildsemi.com