NM27C010 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – 1,048,576-Bit (128K x 8) High Performance CMOS EPROM

October 1998
NM27C010
1,048,576-Bit (128K x 8) High Performance
CMOS EPROM
General Description
The NM27C010 is a high performance, 1,048,576-bit Electrically
Programmable UV Erasable Read Only Memory. It is organized
as 128K-words of 8 bits each. Its pin-compatibility with byte-wide
JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.
The “Don’t Care” feature during read operations allows memory
expansions from 1M to 8M bits with no printed circuit board
changes.
The NM27C010 can directly replace lower density 28-pin EPROMs
by adding an A16 address line and V_CC jumper. During the normal
read operation PGM and V_PP are in a “Don’t Care” state which
allows higher order addresses, such as A17, A18, and A19 to be
connected without affecting the normal read operation. This
allows memory upgrades to 8M bits without hardware changes.
The NM27C010 is also offered in a 32-pin plastic DIP with the
same upgrade path.
The NM27C010 provides microprocessor-based systems exten-
sive storage capacity for large portions of operating system and
application software. Its 70 ns access time provides no-wait-state
operation with high-performance CPUs. The NM27C010 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
The NM27C010 is manufactured using Fairchild’s advanced
CMOS AMG™ EPROM technology.
The NM27C010 is one member of a high density EPROM Family
which range in densities up to 4 Megabit.
Features
s High performance CMOS
— 70 ns access time
s Fast turn-off for microprocessor compatibility
s Simplified upgrade path
— V_PP and PGM are “Don’t Care” during normal read
operation
s Manufacturers identification code
s Fast programming
s JEDEC standard pin configurations
— 32-pin PDIP package
— 32-pin PLCC package
— 32-pin CERDIP package
Block Diagram
VCC
GND
VPP
OE
CE
PGM
Output Enable,
Chip Enable, and
Program Logic
Data Outputs O0 - O7
Output
Buffers
Y Decoder
A0 - A16
Address
Inputs
X Decoder
1,048,576-Bit
Cell Matrix
© 1998 Fairchild Semiconductor Corporation
1
DS010798-1
www.fairchildsemi.com
NM27C010 ver. 1.1