NM25C041 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI™) Synchronous Bus)

March 1999
NM25C041
4K-Bit Serial Interface CMOS EEPROM (Serial
Peripheral Interface (SPI™) Synchronous Bus)
General Description
The NM25C041 is a 4096-bit MODE 1 SPI (Serial Peripheral
Interface) CMOS EEPROM which is designed for high-reliability
non-volatile data storage applications. The SPI interface features
a byte-wide format (all data is transferred in 8-bit words) to
interface with the Motorola 68HC11 microprocessor, or equivalent,
at a 2.1MHz clock transfer rate. (This interface is considered the
fastest serial communication method.) This 4-wire SPI interface
allows the end user full EEPROM functionality while keeping pin
count and space requirements low for maximum PC board space
utilization.
The SPI interface requires four I/O pins on each EEPROM device:
Chip Select (CS), Clock (SCK), Serial Data In (SI), and Serial Data
Out (SO), as well as 2 other control pins: Write Protect (WP) and
HOLD (HOLD). The Write Protect pin can be used to disable the
Write operation and the HOLD pin is used to interrupt the SI
datastream and place the device in a Hold state during micropro-
cessor instruction generation. Please refer to the following dia-
grams and description for more details.
All programming cycles are completely self-timed and do not
require an ERASE, or similar setup, before programming any cells.
Programming can be performed in 3 modes, address (byte) write,
page (4 addresses/bytes) write or partial page write. Furthermore,
the EEPROM is provided with 4 levels of write protection wherein
the data, once programmed, cannot be altered. This is controlled
by the Status Register and is described in greater detail within this
datasheet. In order to prevent spurious programming, the EEPROM
has both a Write Enable command, which is immediately disabled
after each programming operation, and a Write Protect (WP) pin,
which must be pulled HIGH to program.
Features
s 2.1 MHz clock rate @ 2.7V to 5.5V
s 4096 bits organized as 512 x 8
s Multiple chips on the same 3 wire bus with separate chip
select lines
s Self-timed programming cycle
s Simultaneous programming of 1 to 4 bytes at a time
s Status register can be polled during programming to monitor
RDY/BUSY
s Both the Write Protect (WP) pin and 'auto-write disable after
programming' provides hardware and software write
protection
s Block write protect feature to protect against accidental
writes
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP and 8-pin SO
Block Diagram
CS
Instruction
VCC
HOLD
Decoder
VSS
SCK
Control Logic
SI
Instruction
Register
and Clock
Generators
WP
Address
Counter/
Register
Decoder
1 of 512
Program
Enable
VPP
EEPROM Array
4096 Bits
(512 x 8)
High Voltage
Generator
and
Program
Timer
Read/Write Amps
Data In/Out Register
8 Bits
Data Out
Buffer
SO
SPI™ is a trademark of Motorola Corporation.
Non-Volatile
Status Register
DS800002-1
© 1999 Fairchild Semiconductor Corporation
1
NM25C041 Rev. D.1
www.fairchildsemi.com