NM24C65 Datasheet, PDF (1/11 Pages) Fairchild Semiconductor – 64K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect

PRELIMINARY
March 1999
NM24C65
64K-Bit Extended 2-Wire Bus Interface
Serial EEPROM with Write Protect
General Description:
The NM24C65 devices are 65,536 bits of CMOS nonvolatile
electrically erasable memory. These devices offer the designer
different low voltage and low power options, and they conform to
all in the Extended IIC 2-wire protocol. Furthermore, they are
designed to minimize device pin count and simplify PC board
layout requirements.
The upper half of the memory can be disabled (Write Protection)
by connecting the WP pin to V_CC. This section of memory then
becomes ROM.
This communication protocol uses CLOCK (SCL) and DATA I/O
(SDA) lines to synchronously clock data between the master (for
example a microprocessor) and the slave EEPROM device(s).
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption.
Features:
s Extended operating voltage 2.7V – 5.5V
s 400 KHz clock frequency (F) at 2.7V - 5.5V
s 200µA active current typical
10µA standby current typical
1µA standby typical (L)
0.1µA standby typical (LZ)
s IIC compatible interface
– Provides bidirectional data transfer protocol
s 32 byte page write mode
– Minimizes total write time per byte
s Self timed write cycle
Typical write cycle time of 6ms
s Hardware write protect for upper block
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin SO, 8-pin DIP
s Low V_CC programming lockout (3.8V - on Standard V_CC
devices only).
Block Diagram
VCC
WP
SDA
SCL
A2
A1
A0
WRITE
LOCKOUT
START
STOP
LOGIC
START CYCLE
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
XDEC
H.V. GENERATION
TIMING &CONTROL
E2PROM
ARRAY
R/W
YDEC
CK
DIN
DATA REGISTER
DOUT
© 1999 Fairchild Semiconductor Corporation
1
NM24C65 Rev. C.3
DS500042-1
www.fairchildsemi.com