NDS9959 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – Dual N-Channel Enhancement Mode Field Effect Transistor

NDS9959
Dual N-Channel Enhancement Mode Field Effect Transistor
February 1996
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications such
as DC motor control and DC/DC conversion where fast
switching, low in-line power loss, and resistance to transients
are needed.
Features
2.0A, 50V. R_DS(ON) = 0.3Ω @ V_GS = 10V
High density cell design for extremely low R_DS(ON).
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
_________________________________________________________________________________
5
4
6
3
7
2
8
1
Absolute Maximum Ratings
Symbol Parameter
T_A = 25°C unless otherwise noted
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain Current - Continuous @ T_A = 25°C
(Note 1a)
- Continuous @ T_A = 70°C
(Note 1a)
- Pulsed @ T_A = 25°C
P_D
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
(Note 1c)
R_θJA
R_θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1997 Fairchild Semiconductor Corporation
NDS9959
50
± 20
± 2.0
± 1.6
±8
2
1.6
1
0.9
-55 to 150
78
40
Units
V
V
A
W
°C
°C/W
°C/W
NDS9959.SAM