NDS9958 Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – Dual N & P-Channel Enhancement Mode Field Effect Transistor

February 1996
NDS9958
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
Features
These dual N- and P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications such
as notebook computer power management, Half bridge motor
control, cellular phone, and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
N-Channel 3.5A, 20V, R_DS(ON) = 0.1Ω @ V_GS = 10V.
P-Channel -3.5A , -20V, R_DS(ON) = 0.1Ω @ V_GS = -10V.
High density cell design for extremely low R_DS(ON).
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
_______________________________________________________________________________
5
4
6
3
7
2
8
1
Absolute Maximum Ratings
Symbol Parameter
T_A = 25°C unless otherwise noted
N-Channel
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain Current - Continuous T_A = 25°C
- Continuous T_A = 70°C
- Pulsed T_A = 25°C
P_D
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1a)
(Note 1a)
20
± 20
± 3.5
± 2.8
± 14
(Note 1b)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
(Note 1c)
R_θJA
R_θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
2
1.6
1
0.9
-55 to 150
78
40
P-Channel
-20
± 20
± 3.5
± 2.8
± 14
© 1997 Fairchild Semiconductor Corporation
Units
V
V
A
W
°C
°C/W
°C/W
NDS9958.SAM