NDS8433 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – Single P-Channel Enhancement Mode Field Effect Transistor

June 1996
NDS8433
Single P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
Features
-5.2A, -20V. R_DS(ON) = 0.055Ω @ V_GS = -4.5V
R_DS(ON) = 0.075Ω @ V_GS = -2.7V.
High density cell design for extremely low R_DS(ON).
High power and current handling capability in a widely used
surface mount package.
____________________________________________________________________________________________
5
4
6
3
7
2
8
1
Absolute Maximum Ratings T_A = 25°C unless otherwise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain Current - Continuous
- Pulsed
(Note 1a)
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
R_θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1997 Fairchild Semiconductor Corporation
NDS8433
-20
-8
-5.2
-20
2.5
1.2
1
-55 to 150
50
25
Units
V
V
A
W
°C
°C/W
°C/W
NDS8433 Rev. B1