NDS352P Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – P-Channel Logic Level Enhancement Mode Field Effect Transistor

March 1996
NDS352P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management, portable
electronics, and other battery powered circuits where fast
high-side switching, and low in-line power loss are
needed in a very small outline surface mount package.
-0.85A, -20V. R_DS(ON) = 0.5Ω @ V_GS = -4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R_DS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
____________________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol Parameter
T_A = 25°C unless otherwise noted
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Maximum Drain Current - Continuous
- Pulsed
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1a)
(Note 1b)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
R_θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
NDS352P
-20
±12
±0.85
±10
0.5
0.46
-55 to 150
250
75
© 1997 Fairchild Semiconductor Corporation
Units
V
V
A
W
°C
°C/W
°C/W
NDS352P Rev. F1