NDS352AP Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – P-Channel Logic Level Enhancement Mode Field Effect Transistor

February 1997
NDS352AP
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P -Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage applications
such as notebook computer power management, portable
electronics, and other battery powered circuits where fast
high-side switching, and low in-line power loss are needed in a
very small outline surface mount package.
Features
-0.9 A, -30 V. R_DS(ON) = 0.5 Ω @ V_GS = -4.5 V
R_DS(ON) = 0.3 Ω @ V_GS = -10 V.
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOT^TM-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low R_DS(ON).
Exceptional on-resistance and maximum DC current
capability.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol Parameter
T_A = 25°C unless otherwise noted
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Maximum Drain Current - Continuous
- Pulsed
(Note 1a)
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
R_θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1997 Fairchild Semiconductor Corporation
NDS352AP
-30
±20
±0.9
±10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
NDS352AP Rev.D