NDP7061L Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – N-Channel Logic Level Enhancement Mode Field Effect Transistor

June 1996
NDP7061L / NDB7061L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These logic level N-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly suited for
low voltage applications such as automotive, DC/DC
converters, PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss, and
resistance to transients are needed.
60 A, 60 V. R_DS(ON) = 0.018 Ω @ V_GS= 5 V
R_DS(ON) = 0.013 Ω @ V_GS= 10 V.
Low drive requirements allowing operation directly from logic
drivers. V_GS(TH) < 2.0V.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R_DS(ON).
TO-220 and TO-263 (D²PAK) package for both through hole
and surface mount applications.
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D
G
S
Absolute Maximum Ratings
Symbol Parameter
T_C = 25°C unless otherwise noted
NDP7061L
V_DSS
Drain-Source Voltage
V_DGR
Drain-Gate Voltage (R_GS < 1 MΩ)
V_GSS
Gate-Source Voltage - Continuous
- Nonrepetitive (t_P < 50 µs)
I_D
Drain Current - Continuous
- Pulsed
P_D
Maximum Power Dissipation @ T_C = 25°C
Derate above 25°C
T_J,T_STG Operating and Storage Temperature Range
60
60
± 16
± 25
60
180
130
0.87
-65 to 175
NDB7061L
Units
V
V
V
A
W
W/°C
°C
© 1997 Fairchild Semiconductor Corporation
NDP7061L Rev.C1