NDP7061 Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – N-Channel Enhancement Mode Field Effect Transistor

May 1996
NDP7061 / NDB7061
N-Channel Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
64A, 60V. R_DS(ON) = 0.016Ω @ V_GS=10V.
Critical DC electrical parameters specified at elevated
temperature.
superior switching performance, and withstand high energy
Rugged internal source-drain diode can eliminate the need
pulses in the avalanche and commutation modes. These
for an external Zener diode transient suppressor.
devices are particularly suited for low voltage applications such
as automotive, DC/DC converters, PWM motor controls, and
175°C maximum junction temperature rating.
other battery powered circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
High density cell design for extremely low R_DS(ON).
TO-220 and TO-263 (D²PAK) package for both through hole
and surface mount applications.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol Parameter
T_C = 25°C unless otherwise noted
NDP7061
V_DSS
Drain-Source Voltage
V_DGR
Drain-Gate Voltage (R_GS < 1 MΩ)
V_GSS
Gate-Source Voltage - Continuous
- Nonrepetitive (t_P < 50 µs)
I_D
Drain Current - Continuous
- Pulsed
P_D
Maximum Power Dissipation @ T_C = 25°C
Derate above 25°C
T_J,T_STG
T_L
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
60
60
± 20
± 40
64
190
130
0.87
-65 to 175
275
NDB7061
Units
V
V
V
A
W
W/°C
°C
°C
© 1997 Fairchild Semiconductor Corporation
NDP7061 Rev. C / NDB7061 Rev. D