NDP7052 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – N-Channel Enhancement Mode Field Effect Transistor

June 1997
NDP7052 / NDB7052
N-Channel Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process has
been especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation modes.
These devices are particularly suited for low voltage
applications such as automotive, DC/DC converters, PWM
motor controls, and other battery powered circuits where fast
switching, low in-line power loss, and resistance to transients
are needed.
75 A, 50 V. R_DS(ON) = 0.01 Ω @ V_GS= 10 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R_DS(ON).
TO-220 and TO-263 (D²PAK) package for both through hole
and surface mount applications.
________________________________________________________________________________
D
G
Absolute Maximum Ratings T_C = 25°C unless otherwise noted
Symbol Parameter
NDP7052
V_DSS
Drain-Source Voltage
V_DGR
Drain-Gate Voltage (R_GS < 1 MΩ)
V_GSS
Gate-Source Voltage - Continuous
- Nonrepetitive (t_P < 50 µs)
I_D
Drain Current - Continuous
- Pulsed
P_D
Total Power Dissipation @ T_C = 25°C
Derate above 25°C
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJC
R_{θ JA}
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
© 1997 Fairchild Semiconductor Corporation
S
50
50
±20
±40
75
225
150
1
-65 to 175
NDB7052
1
62.5
Units
V
V
V
A
W
W/°C
°C
°C/W
°C/W
NDP7052 Rev.B1