NDP6030PL Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – P-Channel Logic Level Enhancement Mode Field Effect Transistor

June 1997
NDP6030PL / NDB6030PL
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as DC/DC converters and high efficiency
switching circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
Features
-30
A,
-30
V.
R_DS(ON)
R_DS(ON)
=
=
0.042
0.025
Ω
Ω
@
@
V_GS= -4.5 V
V_GS= -10 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low R_DS(ON).
175°C maximum junction temperature rating.
________________________________________________________________________________
S
G
D
Absolute Maximum Ratings
Symbol Parameter
T_C = 25°C unless otherwise noted
NDP6030PL
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain Current - Continuous
- Pulsed
P_D
Total Power Dissipation @ T_C = 25°C
Derate above 25°C
T_J,T_STG
T_L
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJC
Thermal Resistance, Junction-to-Case
R_θJA
Thermal Resistance, Junction-to-Ambient
© 1997 Fairchild Semiconductor Corporation
-30
±16
-30
-90
75
0.5
-65 to 175
275
NDB6030PL
-65 to 175
2
62.5
Units
V
V
A
W
°C
°C
°C
°C/W
°C/W
NDP6030PL Rev.B1