NDP6030L Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – N-Channel Logic Level Enhancement Mode Field Effect Transistor

June 1996
NDP6030L / NDB6030L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited
for low voltage applications such as DC/DC converters
and high efficiency switching circuits where fast
switching, low in-line power loss, and resistance to
transients are needed.
52 A, 30 V. R_DS(ON) = 0.0135 Ω @ V_GS=10 V
R_DS(ON) = 0.020 Ω @ V_GS=4.5 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low R_DS(ON).
175°C maximum junction temperature rating.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol Parameter
T_C = 25°C unless otherwise noted
NDP6030L
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain Current - Continuous
- Pulsed
P_D
Total Power Dissipation @ T_C = 25°C
Derate above 25°C
T_J,T_STG
T_L
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
THERMAL CHARACTERISTICS
R_θJC
R_θJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
30
± 16
52
156
75
0.5
-65 to 175
275
NDB6030L
2
62.5
© 1998 Fairchild Semiconductor Corporation
Units
V
V
A
W
W/°C
°C
°C
°C/W
°C/W
NDP6030L Rev.E