NDP6020P Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – P-Channel Logic Level Enhancement Mode Field Effect Transistor

September 1997
NDP6020P / NDB6020P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly suited for
low voltage applications such as automotive, DC/DC
converters, PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss, and
resistance to transients are needed.
Features
-24
A,
-20
V.
R_DS(ON)
R_DS(ON)
R_DS(ON)
=
=
=
000...0007755^{ΩΩΩ@@@VVG}V^GSGS==_S=-2-4-.27.5.5VV.V. .
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R_DS(ON).
TO-220 and TO-263 (D²PAK) package for both through
hole and surface mount applications.
________________________________________________________________________________
S
G
D
Absolute Maximum Ratings T_C = 25°C unless otherwise noted
Symbol Parameter
NDP6020P
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain Current - Continuous
- Pulsed
P_D
Total Power Dissipation @ T_C = 25°C
Derate above 25°C
T_J,T_STG Operating and Storage Temperature Range
-20
±8
-24
-70
60
0.4
-65 to 175
NDB6020P
Units
V
V
A
W
W/°C
°C
© 1997 Fairchild Semiconductor Corporation
NDP6020P Rev.C1