NDP4050L Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – N-Channel Logic Level Enhancement Mode Field Effect Transistor

April 1996
NDP4050L / NDB4050L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These logic level N-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly suited for
low voltage applications such as automotive, DC/DC
converters, PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss, and
resistance to transients are needed.
15A, 50V. R_DS(ON) = 0.1Ω @ V_GS = 5V
Low drive requirements allowing operation directly from logic
drivers. V_GS(TH) < 2.0V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R_DS(ON).
TO-220 and TO-263 (D²PAK) package for both through hole
and surface mount applications.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol Parameter
T_C = 25°C unless otherwise noted
NDP4050L
V_DSS
Drain-Source Voltage
V_DGR
Drain-Gate Voltage (R_GS < 1 MΩ)
V_GSS
Gate-Source Voltage - Continuous
- Nonrepetitive (t_P < 50 µs)
I_D
Drain Current - Continuous
- Pulsed
P_D
Total Power Dissipation @ T_C = 25°C
Derate above 25°C
T_J,T_STG
T_L
Operating and Storage Temperature
Maximum lead temperature for soldering
purposes, 1/8" from case for 5 seconds
50
50
± 16
± 25
15
45
50
0.33
-65 to 175
275
NDB4050L
Units
V
V
V
A
W
W/°C
°C
°C
© 1997 Fairchild Semiconductor Corporation
NDP4050L Rev. B / NDB4050L Rev. C