NDH8521C Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – Dual N & P-Channel Enhancement Mode Field Effect Transistor

May 1997
NDH8521C
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
Features
These dual N- and P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
N-Ch 3.8 A, 30 V, R_DS(ON)=0.033Ω @ V_GS=10 V
R_DS(ON)=0.05 Ω @ V_GS=4.5 V
P-Ch -2.7 A, -30 V,R_DS(ON)=0.07 Ω @ V_GS=-10 V
R_DS(ON)=0.115 Ω @ V_GS=-4.5 V.
Proprietary SuperSOT^TM-8 package design using copper lead
frame for superior thermal and electrical capabilities.
High density cell design for extremely low R_DS(ON).
Exceptional on-resistance and maximum DC current
capability.
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5
4
6
3
7
2
8
1
Absolute Maximum Ratings
Symbol Parameter
T_A= 25°C unless otherwise noted
N-Channel
V_DSS
Drain-Source Voltage
30
V_GSS
Gate-Source Voltage
±20
I_D
Drain Current - Continuous
(Note 1)
3.8
- Pulsed
10.5
P_D
Power Dissipation for Single Operation (Note 1)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1)
R_θJC
Thermal Resistance, Junction-to-Case (Note 1)
0.8
-55 to 150
156
40
P-Channel
-30
±20
-2.7
-8
Units
V
V
A
W
°C
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDH8521C Rev.C