NDH8321C Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – Dual N & P-Channel Enhancement Mode Field Effect Transistor

January 1999
NDH8321C
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
Features
These dual N- and P -Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and other battery powered circuits where fast
switching, low in-line power loss, and resistance to
transients are needed.
N-Ch 3.8 A, 20 V, R_DS(ON)=0.035 Ω @ V_GS= 4.5 V
R_DS(ON)=0.045 Ω @ V_GS=2.7 V
P-Ch -2.7 A, -20V, R_DS(ON)=0.07Ω @ V_GS= -4.5 V
R_DS(ON)=0.095 Ω @ V_GS= -2.7 V.
Proprietary SuperSOT^TM-8 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R_DS(ON).
Exceptional on-resistance and maximum DC current
capability.
_______________________________________________________________________________
D2
D2
D1
D1
SuperSOT ^TM-8
Mark: .8321C
S2
G2
S1
G1
5
4
6
3
7
2
8
1
Absolute Maximum Ratings T_A= 25°C unless otherwise noted
Symbol Parameter
N-Channel
V_DSS
Drain-Source Voltage
20
V_GSS
Gate-Source Voltage
±8
I_D
Drain Current - Continuous
(Note 1)
3.8
- Pulsed
15
P_D
Power Dissipation for Single Operation (Note 1)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1)
R_θJC
Thermal Resistance, Junction-to-Case (Note 1)
0.8
-55 to 150
156
40
P-Channel
-20
±8
-2.7
-10
Units
V
V
A
W
°C
°C/W
°C/W
© 1999 Fairchild Semiconductor Corporation
NDH8321C Rev.C1