NDC7003P Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – Dual P-Channel Enhancement Mode Field Effect Transistor

March 1996
NDC7003P
Dual P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual P-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been designed to minimize
on-state resistance, provide rugged and reliable
performance and fast switching. This product is
particularly suited to low voltage applications requiring a
low current high side switch.
Features
-0.34A, -50V. R_DS(ON)= 5Ω @ V_GS=-10V.
High density cell design for low R_DS(ON).
Proprietary SuperSOT^TM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High saturation current.
____________________________________________________________________________________________
SOT-6 (SuperSOT^TM-6)
4
3
5
2
6
1
Absolute Maximum RatingsT_A = 25°C unless otherwise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain Current - Continuous
- Pulsed
(Note 1a)
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
R_θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
NDC7003P
-50
-20
-0.34
-1
0.96
0.9
0.7
-55 to 150
130
60
Units
V
V
A
W
°C
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation