NDC632P Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – P-Channel Logic Level Enhancement Mode Field Effect Transistor

June1996
NDC632P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode
power field effect transistors are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is
especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as notebook computer power
management and other battery powered circuits
where fast high-side switching, and low in-line power
loss are needed in a very small outline surface
mount package.
Features
-2.7A, -20V. R_DS(ON) = 0.14Ω @ V_GS = -4.5V
R_DS(ON) = 0.2Ω @ V_GS = -2.7V.
Proprietary SuperSOT^TM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R_DS(ON).
Exceptional on-resistance and maximum DC current
capability.
___________________________________________________________________________________________
SuperSOT^TM-6
4
3
5
2
6
1
Absolute Maximum Ratings
Symbol Parameter
T_A = 25°C unless otherwise noted
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain Current - Continuous
- Pulsed
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
R_θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1997 Fairchild Semiconductor Corporation
NDC632P
-20
-8
-2.7
-10
1.6
1
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
NDC632P Rev. B1