NDC631N Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – N-Channel Logic Level Enhancement Mode Field Effect Transistor

NDC631N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
July 1996
General Description
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications in
notebook computers, portable phones, PCMICA cards, and
other battery powered circuits where fast switching, and low
in-line power loss are needed in a very small outline surface
mount package.
Features
4.1 A, 20 V. R_DS(ON) = 0.06 Ω @ V_GS = 4.5 V
R_DS(ON) = 0.075 Ω @ V_GS =2.7 V.
Proprietary SuperSOT^TM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R_DS(ON).
Exceptional on-resistance and maximum DC current
capability.
____________________________________________________________________________________________
Absolute Maximum Ratings T_A = 25°C unless otherwise note
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain Current - Continuous
- Pulsed
(Note 1a)
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
R_θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
4
3
5
2
6
1
NDC631N
20
8
4.1
15
1.6
1
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDC631N Rev.D1