MM74C89 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – 64-Bit 3-STATE Random Access Read/Write Memory

October 1987
Revised January 1999
MM74C89
64-Bit 3-STATE Random Access Read/Write Memory
General Description
The MM74C89 is a 16-word by 4-bit random access read/
write memory. Inputs to the memory consist of four address
lines, four data input lines, a write enable line and a mem-
ory enable line. The four binary address inputs are
decoded internally to select each of the 16 possible word
locations. An internal address register latches the address
information on the positive to negative transition of the
memory enable input. The four 3-STATE data output lines
working in conjunction with the memory enable input pro-
vide for easy memory expansion.
Address Operation: Address inputs must be stable t_SA
prior to the positive to negative transition of memory
enable. It is thus not necessary to hold address information
stable for more than t_HA after the memory is enabled (posi-
tive to negative transition of memory enable).
Write Operation: Information present at the data inputs is
written into the memory at the selected address by bringing
write enable and memory enable LOW.
Read Operation: The complement of the information
which was written into the memory is non-destructively
read out at the four outputs. This is accomplished by
selecting the desired address and bringing memory enable
LOW and write enable HIGH.
When the device is writing or disabled the output assumes
a 3-STATE (Hi-z) condition.
Features
s Wide supply voltage range: 3.0V to 15V
s Guaranteed noise margin: 1.0V
s High noise immunity: 0.45 V_CC (typ.)
s Low power TTL compatibility:
fan out of 2 driving 74L
s Low power consumption: 100 nW/package (typ.)
s Fast access time: 130 ns (typ.) at V_CC = 10V
s 3-STATE output
Note: The timing is different than the DM7489 in that a positive to negative
transition of the memory enable must occur for the memory to be selected.
Ordering Code:
Order Number
MM74C89N
Package Number Package Description
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Connection Diagram
Pin Assignments for DIP
Truth Table
ME WE Operation
Condition of Outputs
L L Write
3-STATE
L H Read
Complement of Selected Word
H L Inhibit, Storage 3-STATE
H H Inhibit, Storage 3-STATE
Top View
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