ML6554 Datasheet, PDF (1/14 Pages) Fairchild Semiconductor – 3A Bus Termination Regulator

ML6554
3A Bus Termination Regulator
www.fairchildsemi.com
Features
• Can source and sink up to 3A, no heat sink required
• Integrated Power MOSFETs
• Generates termination voltages for DDR SDRAM,
SSTL-2 SDRAM, SGRAM, or equivalent memories
• Generates termination voltages for active termination
schemes for DDR SDRAM, GTL+, Rambus, VME,
LV-TTL, HSTL, PECL and other high speed logic
• V_REF input available for external voltage divider
• Separate voltages for V_CCQ and PV_DD
• Buffered V_REF output
• V_OUT of ±3% or less at 3A
• Minimum external components
• Shutdown for standby or suspend mode operation
• 0° to +70°C and -40° to +85°C temperature ranges
available
• Thermal Shutdown ≈ 130ºC
Block Diagram
Description
The ML6554 switching regulator is designed to convert volt-
age supplies ranging from 2.3V to 4V into a desired output
voltage or termination voltage for various applications. The
ML6554 can be implemented to produce regulated output
voltages in two different modes. In the default mode, when
the V_REF pin is open, the ML6554 output voltage is 50% of
the voltage applied to V_CCQ. The ML6554 can also be used
to produce various user-defined voltages by forcing a voltage
on the VREF_IN pin. In this case, the output voltage follows
the input VREF_IN voltage. The switching regulator is capa-
ble of sourcing or sinking up to 3A of current while regulat-
ing an output V_TT voltage to within 3% or less.
The ML6554, used in conjunction with series termination
resisitors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed
backplane designs. The voltage output of the regulator can
be used as a termination voltage for other bus interface
standards such as DDR SDRAM, SSTL, CMOS, Rambus^™,
GTL+, VME, LV-CMOS, LV-TTL, HSTL and PECL.
15
16
14
VCCQ AV_CC VREFOUT
200kΩ
VREFIN
11
200kΩ
AGND
13
–
+
VREF BUFFER
OSCILLATOR/
RAMP
GENERATOR
ERROR AMP
+
–
VFB
10
1
VDD
9
VDD
12
SHDN
2
7
PVDD1 PVDD2
VL1
(VOUT)
3
SQ
–
RQ
+
RAMP
COMPARATOR
6
VL2
(VOUT)
DGND
8
PGND1 PGND2
4
5
REV. 1.1.3 3/8/02