ML6553 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – Bus Termination Regulator

ML6553
Bus Termination Regulator
www.fairchildsemi.com
Features
• Can source and sink up to 1A
• Generates termination voltages for DDR SDRAM,
SSTL_2 SDRAM, SGRAM, or equivalent memories
• Generates termination voltages for active termination
schemes for GTL+, DDR, Rambus^™, VME, LV-TTL,
PECL and other high speed logic
• VL regulated to within 3% at 800mA
• Minimum external components. Requires no feedback
compensation
• Fixed frequency operation for easier system integration
• Lower power consumption than passive, resistor divider
termination, reducing heat by as much as 50%
• Separate voltages for VCCQ and PVDD
General Description
The ML6553 switching regulator is designed to convert
voltage supplies ranging from 2.0V to 3.6V into a desired
output voltage or termination voltage for various applica-
tions. The ML6553 can be implemented to produce
regulated output voltages in two different modes. In the
default mode, the output is 50% of voltage applied to VCCQ.
The switching regulator is capable of sourcing or sinking up
to 1A of current.
The ML6553, used in conjunction with series termination
resistors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed back-
plane designs. The voltage output of the regulator can be
used as a termination voltage for other bus interface
standards such as SSTL, DDR, Rambus^™, GTL+, VME,
LV-CMOS, LV-TTL, P-ECL, and CMOS.
Block Diagram
1
VCCQ
4
AVCC
CLK
190kΩ
OSCILLATOR/
RAMP GENERATOR ^RAMP
VCCQ/2
2
BUFFER
AGND
3
190kΩ
+
VINTEG
–
SQ
–
RQ
+
PWM
COMPARATOR
5
PVDD
Q1
VL
6
VL
7
Q2
DGND
8
REV. 1.0.2 3/21/01