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ML4800CP Datasheet, PDF (1/14 Pages) Fairchild Semiconductor – Internally synchronized leading-edge PFC and trailing-edge PWM in one IC
www.fairchildsemi.com
ML4800
Power Factor Correction and PWM Controller
Combo
Features
• Internally synchronized leading-edge PFC and trailing-
edge PWM in one IC
• TriFault Detect™ for UL1950 compliance and enhanced
safety
• Slew rate enhanced transconductance error amplifier for
ultra-fast PFC response
• Low power: 200µA startup current, 5.5mA operating
current
• Low total harmonic distortion, high PF
• Reduced ripple current in storage capacitor between PFC
and PWM sections
• Average current, continuous boost leading edge PFC
• PWM configurable for current-mode or voltage mode
operation
• Current fed gain modulator for improved noise immunity
• Overvoltage and brown-out protection, UVLO, and soft
start
General Description
The ML4800 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching FETs,
and results in a power supply that fully complies with
IEC1000-3-2 specification. Intended as a BiCMOS version
of the industry-standard ML4824, the ML4800 includes
circuits for the implementation of leading edge, average
current, “boost” type power factor correction and a trailing
edge, pulse width modulator (PWM). It also includes a
TriFault Detect™ function to help ensure that no unsafe
conditions will result from single component failure in the
PFC. Gate-drivers with 1A capabilities minimize the need
for external driver circuits. Low power requirements improve
efficiency and reduce component costs.
An over-voltage comparator shuts down the PFC section in
the event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brownout
protection. The PWM section can be operated in current or
voltage mode, at up to 250kHz, and includes an accurate
50% duty cycle limit to prevent transformer saturation.
Block Diagram
16
VEAO
1
IEAO
VFB
15
2.5V
IAC
2
VRMS
4
ISENSE
3
VEA
-
+
1.6kΩ IEA
+
-
GAIN
MODULATOR
1.6kΩ
POWER FACTOR CORRECTOR
0.5V
+
TRI-FAULT
+
-
2.75V
OVP
+
-
-
-1V +
-
PFC ILIMIT
RAMP 1
7
OSCILLATOR
RAMP 2
8
DUTY CYCLE
LIMIT
VCC
17V
13
VCC
7.5V
REFERENCE
VREF
14
SQ
RQ
SQ
PFC OUT
12
RQ
VDC
6
VCC
SS
5
25µA
1.25V
DC ILIMIT VREF
9
-
+
-
+
VFB
2.45V
VIN OK
-
+
1.0V
-
+
DC ILIMIT
PULSE WIDTH MODULATOR
VCC
SQ
RQ
PWM OUT
11
UVLO
REV. 1.0.5 9/25/01