ML2021 Datasheet, PDF (1/11 Pages) Fairchild Semiconductor – Telephone Line Equalizer

ML2021
Telephone Line Equalizer
www.fairchildsemi.com
Features
• Slope, height, and bandwidth adjustable
• Optimized group delays (500 Hz to 6.4 kHz)
• On chip anti-alias filter
• Bypass mode
• Low supply current 6 mA typical from ±5V supplies
• TTL / CMOS compatible interface
• Double buffered data latch
• Selectable master clock 1.544 or 1.536 MHz
• Synchronous or asynchronous data loading capability
• Compatible with ML2003 and ML2004 logarithmic
gain/attenuator
General Description
The ML2021 is a monolithic analog line equalizer for tele-
phone applications. The ML2021 consists of a switched
capacitor filter that realizes a family of frequency response
curves optimized for telephone line equalization while mini-
mizing group delay.
The ML2021 consists of a continuous anti-aliasing filter,
three programmable switched capacitor equalization filters,
an output smoothing filter, a 600Ω driver, and a digital
section for the serial interface.
The equalization filters adjust the slope, height, and band-
width of the frequency response. The desired frequency
response is programmed by a digital 14-bit serial input data
stream.
Block Diagram
CLKSEL
CLK
CLOCK
GENERATOR
VCC AGND VSS
SMOOTHING
FILTER
VOUT
VIN
ANTIALIAS
LO PASS
MUX
PDN
LATI
SID
SLOPE
HEIGHT BANDPASS
1
SECTION SECTION SECTION
5
4
4
14-BIT LATCH
14
14-BIT SHIFT REGISTER
GND
SOD
SCK
LATO
Pin Connections
ML2021
16-PIN DIP
CLKSEL 1
SID 2
NC 3
LATO 4
16 VCC
15 PDN
14 VOUT
13 AGND
SCK 5
NC 6
SOD 7
12 VIN
11 VSS
10 LATI
CLK 8
9 GND
TOP VIEW
ML2021
18-PIN SOIC
CLKSEL
SID
NC
LATO
SCK
NC
SOD
CLK
GND
1
18
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
TOP VIEW
VCC
PDN
VOUT
AGND
NC
VIN
NC
VSS
LATI
REV. 1.1.1 3/19/01