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J270 Datasheet, PDF (1/3 Pages) Calogic, LLC – P-Channel JFET
J270
P-Channel Switch
• This device is designed for low level analog switching sample and hold
circuits and chopper stabilized amplifiers.
• Sourced from process 88.
1
TO-92
1. Drain 2. Gate 3. Source
Absolute Maximum Ratings* Ta=25°C unless otherwise noted
Symbol
Parameter
VDG
Drain-Gate Voltage
VGS
Gate-Source Voltage
IGF
Forward Gate Current
TJ, TSTG
Operating and Storage Junction Temperature Range
* This ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
Ratings
-30
30
50
-55 ~ 150
NOTES:
1) These rating are based on a maximum junction temperature of 150 degrees C.
2) These are steady limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Units
V
V
mA
°C
Electrical Characteristics Ta=25°C unless otherwise noted
Symbol
Parameter
Test Condition
Off Characteristics
V(BR)GSS Gate-Source Breakdwon Voltage
IGSS
Gate Reverse Current
VGS(off)
Gate-Source Cutoff Voltage
On Characteristics
IG = -1.0µA, VDS = 0
VGS = -20V, VDS = 0
VDS = -15V, ID = 1.0nA
IDSS
Zero-Gate Voltage Drain Current *
Small Signal Characteristics
VDS = -15V, VGS = 0
gfs
goss
Forward Transferconductance
Common- Source Output Conductance
VGS = 0V, VDS = 15V, f = 1.0kHz
VGS = 0V, VDS = 15V, f = 1.0kHz
Min.
30
0.5
-2.0
6000
Max. Units
V
200
pA
2.0
V
-15
mA
15000 µmhos
200 µmhos
Thermal Characteristics TA=25°C unless otherwise noted
Symbol
Parameter
PD
Total Device Dissipation
Derate above 25°C
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Max.
350
2.8
125
357
Units
mW
mW/°C
°C/W
°C/W
©2003 Fairchild Semiconductor Corporation
Rev. A, July 2003