ISL9N302AP3 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs

January 2002
ISL9N302AP3
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Applications
• DC/DC converters
Features
• Fast switching
• r_DS(ON) = 0.0019Ω (Typ), V_GS = 10V
• r_DS(ON) = 0.0027Ω (Typ), V_GS = 4.5V
• Q_g (Typ) = 110nC, V_GS = 5V
• Q_gd (Typ) = 31nC
• C_ISS (Typ) = 11000pF
SOURCE
DRAIN
GATE
D
G
DRAIN
(FLANGE)
TO-220AB
MOSFET Maximum Ratings T_A = 25°C unless otherwise noted
Symbol
V_DSS
V_GS
I_D
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Continuous (T_C = 25^oC, V_GS = 10V)
Continuous (T_C = 100^oC, V_GS = 4.5V)
Pulsed
P_D
Power dissipation
Derate above 25^oC
T_J, T_STG Operating and Storage Temperature
Thermal Characteristics
R_θJC
R _{θ JA}
Thermal Resistance Junction to Case TO-220
Thermal Resistance Junction to Ambient TO-220
Package Marking and Ordering Information
Device Marking
N302AP
Device
ISL9N302AP3
Package
TO-220AB
Reel Size
Tube
S
Ratings
30
±20
75
75
Figure 4
345
2.3
-55 to 175
0.43
62
Tape Width
N/A
Units
V
V
A
A
A
W
W/^oC
o_C
o_C/W
o_C/W
Quantity
50
©2002 Fairchild Semiconductor Corporation
Rev. B January 2002